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Activity recognition results on UCF Sports and Holywood2

Table above shows the results, obtained on UCF Sports dataset (http://crcv.ucf.edu/data/UCF_Sports_Action.php). We report recognition rate with respect to the number...


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Computational efficiency and parallel implementation

The developed algorithms are computationally effective and the compositional processing pipeline is well-suited for implementation on massively parallel architectures. Many...


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Motion hierarchy structure

Our model is comprised of three processing stages, as shown in the Figure. The task of the lowest stage (layers...


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Server crash

After experiencing a total server failure, we are back online. We apologize for the inconvenience - we are still in...


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L1: motion features

Layer L1 provides an input to the compositional hierarchy. Motion, obtained in L0 is encoded using a small dictionary.


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Efficient implementation of the model

Work package leader: DCS

In past years, there has been a significant change in nature of performance improvements for consumer grade computers (e.g. personal computers). This is a continuation of a trend, which emerged more than a decade ago, when processor designers refocused from increasing clock speeds to improvements in architecture. For many years, those improvements have been confined to inner structure of modern processors and thus transparent to users and programmers. However, in recent years, new trend has begun to emerge: increasing the number of identical processing units (so­called processor “cores”). Now, CPUs with 4 to 8 cores are available for use in desktop computers. Additionally, massively parallel architectures, such as Nvidia CUDA made significant impact in the field of computer vision [Pock2008, Santner2010, Werlberger2010], offering up to 512 processor cores for highly accelerated computation on a desktop PC. However such performance comes at a price – to harness the benefits of those architectures, algorithms have to be redesigned for parallel execution, which is not a straightforward task [Trobec2009a].

Optimization and efficient implementation have been traditionally seen as tasks, which are best left to the stage, when algorithms were ready to be implemented in practical applications [Šterk2005, Depolli2008]. However, given the recent massive increase in computing power of parallel architectures, purely sequential algorithms are able to use smaller and smaller percentage of the available computer power and are therefore becoming less efficient [Trobec2009b]. With modern eight core CPU, the theoretical speedup limit of parallel implementation is eight, and basic image processing tasks can be sped up by one or two orders of magnitude, if massively parallel architecture, such as CUDA enabled graphic card, is used. This can have a tremendous impact on the basic research in fields like computer vision, where large amounts of data are routinely processed and some tasks, such as training of few layers of hierarchical compositional model, can take several hours. Furthermore, since we will extend the domain of hierarchical compositional models to motion analysis with its added temporal dimension, we expect that the amount of computation will significantly increase. Parallel processing will be used to offset this increase as well. We hypothesize that the parallel heterogeneous architecture consisting of multi­core processor and GPU will achieve the best performance in the proposed project. Accordingly, this work package is comprised of the following tasks:

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